EAN: 4260217681881 - ArtNr.: 320163 - Backplane PCIe Gen3 6 slots

Datasheet

Drawing

Our backplanes extend the number of PCIe slots on a Hostsytsem.


The backplane has a transparent PCIe switch which handles the communication between the PCIe devices and the host transparently. There is no need for drivers and it works on all systems from Windows to MAC OS to Linux.
The "Backplane PCIe Gen3 6 Slots" has one 64GBit/S Uplink ( X8 ) and six 32GBit/s Donwlinks (X4)
Via USB the status can be queried / displayed

There are 3 possible applications for the "Backplane PCIe Gen3 6 Slots

  1. Using a client adapter in the upstream port of a backplane and a host adapter (via miniDP cable) the connection to a free PCIe slot in the Hostsystem is established. This can be a PCIe slot with 4 or 8 lanes, or a M2.M or a M2.E slot. The backplane provides 6 additional PCIe slots to the host system. Plug a host adapter into a PCIe slot. Solutions for PCIe X8, X4, M2e and M2M are available. Connect the host adapter to the client adapter using our smart cables and plug it into the backplane. Host and client adapter will automatically adjust to the cable length ( 0.5 to 6.5M).

  2. Using a Thunderbold adapter in the upstream port to connect an existing Apple/ PC / host system / notebook. The backplane provides 6 PCIe slots to the host PC / notebook.

  3. Via PCIe CPU board as stand alone system. The backplane provides 6 PCIe slots to the PCIe CPU board.

Ideal for:

  • Industrial Automatisation
  • Replacemnet of expensive PICMG 1.3 based CPU Boards and Backplanes, through standard industrial Mainboards + PCIE
  • Expansion + Case
  • Replacemnet of expensive PXI based measurement Devices, through standard industrial PC + PCIE Expansion
  • Measurement
  • Development
  • Web Hosting
  • Apple Tunderbold / PCIe Expansion
  • Notebooks Tunderbold to PCIe Expansionm

  • Upstream: 1x PCI Express 3.0 X8
  • Downstream: 6x PCI Express 3.0 X4
  • Switching capacity: 58Gbps
  • LPower consumption: 15W
  • USB connection
  • Made in Germany
 
Achievable data rates Cable 1 + Cable 2 + Cable 3+4
PCIe Generation1 5 Gbit/s 10 Gbit/s 20 Gbit/s
PCIe Generation1 10 Gbit/s 20 Gbit/s 40 Gbit/s
PCIe Generation1 16 Gbit/s 32 Gbit/s 64 Gbit/s
Note: the PCIe specification only provides for PCIe x1 as a mandatory fallback option.

The backplane provides diagnostics and debug information via USB interface: The API provides the following information:
  • Power consumption,
  • Current of the 12V and 3V3 rails,
  • PCIe link status,
  • temperature,
  • fan status,
  • eye diagram,
  • PCIe slot settings
For PCIe development
  • Transaction Layer Packet (TLP) generator for testing and debugging of links and error handling
  • Real-time eye capture
  • Any-to-any port mirroring for debug purposes
  • External loopback at PHY and TLP layers
  • Errors, statistics, performance, and TLP latency counters

Clientadapter X4 Intern / Extern

  • Up to 4 Lanes PCIe Gen 3 = 32 Gbit
  • For internal case or external PCIe hosts
  • Brackets for Low and Full profile
  • Cable Length: 0,5-6,5m

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Hostadapter X4 Intern / Extern

  • Up to 4 Lanes, 32Gbit
  • for in case or external applications

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Hostadapter X8 Intern / Extern

  • Up to 8 Lanes, 64Gbit
  • for external applications

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Hostadapter M2.M X4

  • Up to 4 Lanes, 32Gbit
  • for in case applications

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Hostadapter M2.E X2

  • Up to2 Lanes, 16Gbit
  • for in case applications

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Cable

  • Length 0,5-6,5m

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