Our backplanes extend the number of PCIe slots on a Host system.
The backplane has a transparent PCIe switch which handles the communication between the PCIe devices and the host transparently.
There is no need for drivers, it works on all systems from Windows to MAC OS to Linux.
The “Backplane PCIe Gen3 6 Slots” has one 64 Gbit/S Uplink (X8) and six 32 Gbit/s Downlinks (X4).
Via USB the status can be queried/displayed.
This Backplane is suitable for Case #2, Case #3 and Case #4 housings.
There are 3 possible applications for the “Backplane PCIe Gen3 6 Slots”:
- Using a client adapter in the upstream port of a backplane and a host adapter (via miniDP cable) the connection to a free PCIe slot in the Hostsystem is established.
This can be a PCIe slot with 4 or 8 lanes, or a M2.M or a M2.E slot. The backplane provides 6 additional PCIe slots to the host system.
Plug a host adapter into a PCIe slot. Solutions for PCIe X8, X4, M2e and M2M are available. Connect the host adapter to the client adapter using our smart cables and plug it into the backplane. Host and client adapter will automatically adjust to the cable length (0.5 to 7.5 m).
- Using a Thunderbold adapter in the upstream port to connect an existing Apple/PC/host system/notebook. The backplane provides 6 PCIe slots to the host PC/notebook.
- Via PCIe CPU board as stand alone-system. The backplane provides 6 PCIe slots to the PCIe CPU board.
- Industrial automatisation
- Replacement of expensive PICMG 1.3 based CPU Boards and Backplanes, through standard industrial Mainboards + PCIE
- Expansion + Case
- Replacement of expensive PXI based measurement devices, through standard industrial PC + PCIE Expansion
- Web Hosting
- Apple Thunderbold/PCIe Expansion
- Notebooks Thunderbold to PCIe Expansion
- Upstream: 1x PCI Express 3.0 X8
- Downstream: 6x PCI Express 3.0 X4
- Switching capacity: 58 Gbps
- Power consumption: 15 W
- USB connection
- Suitable for Case #2, Case #3 and Case #4 housings
- Made in Germany
|Achievable data rates||Cable 1||+ Cable 2||+ Cable 3+4|
|PCIe Generation1||5 Gbit/s||10 Gbit/s||20 Gbit/s|
|PCIe Generation2||10 Gbit/s||20 Gbit/s||40 Gbit/s|
|PCIe Generation3||16 Gbit/s||32 Gbit/s||64 Gbit/s|
The backplane provides diagnostics and debug information via USB interface.
The API provides the following information:
- Power consumption
- Current of the 12 V and 3V3 rails
- PCIe link status
- Fan status
- Eye diagram
- PCIe slot settings
For PCIe development:
- Transaction Layer Packet (TLP) generator for testing and debugging of links and error handling
- Real-time eye capture
- Any-to-any port mirroring for debug purposes
- External loopback at PHY and TLP layers
- Errors, statistics, performance, and TLP latency counters
- Up to 8 lanes, 64 Gbit
- For external applications